1. Field of the Invention
The present invention relates to electronic packaging. While not so limited, the invention finds immediate application as a multilayer ceramic, multi-chip, dual in-line, packaging assembly for semiconductor memory circuitry in high speed data processing circuits.
2. Description of the Prior Art
At present there are commercially available multilayer ceramic dual in-line packaging assemblies.
Likewise the prior art is replete with multichip packaging assemblies. See, for example, U.S. Pat. No. 3,365,620, issued to J. H. Butler, et al. on Jan. 23, 1968; U.S. Pat. No. 3,525,617, issued to K. C. A. Bingham on Aug. 25, 1970; and, U.S. Pat. No. 3,777,221, issued to P. A. Tatusko, et al. on Dec. 4, 1973.
Heretofore attempts at a multilayer ceramic, multi-chip, dual in-line, packaging assembly have met with limited success due to difficulties in achieving requisite circuit density.